1. Field of the Invention
The present invention relates to a fabrication process of a semiconductor capacitive element to be employed in DRAM or so forth. More specifically, the invention relates to a fabrication process of a stack type semiconductor capacitive element which can improve an accumulated charge amount of a lower electrode.
2. Description of the Prior Art
In a semiconductor device, especially in a technology forming a lower electrode of a capacitive element in DRAM or so forth, a technology for forming an HSG (Hemispherical Grain) on the surface of a silicon electrode (an HSG technology) is frequency used, in the recent years.
FIGS. 1A to 1E are sections showing a fabrication process steps of a capacitive element using the HSG technology in sequential order. At first, as shown in FIG. 1A, a silicon oxide layer 11 to be an isolation region is formed in a thickness of 300 nm, by selectively oxidizing the surface of an n-type semiconductor substrate 10. The n-type semiconductor substrate 10 may be an n-type impurity region formed on the surface of the semiconductor substrate.
Next, as shown in FIG. 1B, an amorphous silicon film 12 doped with phosphorous is formed over the entire surface in a thickness of 150 nm, by way of thermal CVD technology. The amorphous silicon film 12 is formed by introducing a 100% SiH.sub.4 gas having flow velocity of 1000 sccm and 1% PH.sub.3 gas diluted by a nitrogen gas, having flow velocity of 10 sccm, and maintaining this at about 530.degree. C. under 1 Torr of pressure, for about one hour. By this deposition condition, the amorphous silicon film 12 having phosphorous concentration of about 5.times.10.sup.19 (atoms/cm.sup.3), is formed.
Next, as shown in FIG. 1C, an HSG, namely a silicon crystal having hemisphere unevenness having a diameter of about 50 to 100 nm, is formed on the surface of the amorphous silicon film 12. Process of fabricating the HSG will be discussed later.
Subsequently, as shown in FIG. 1D, the amorphous silicon film 12 is patterned using lithographic technology and dry etching technology, to form a stack electrode, namely a lower electrode 12a of the capacitive element.
Thereafter, as shown in FIG. 1E, a silicon nitride layer to be a capacitance insulation layer is formed on the lower electrode 12a in a thickness about 7 nm, using a thermal CVD technology. Then, on these surface, an upper electrode 13 of the capacitive element of a polycrystalline silicon layer is formed in a thickness of about 150 nm. Then, for electrically activating, heat treatment is performed under gas atmosphere in the presence of phosphorous oxytrichloride. By this, the stack type semiconductor capacitive element is formed.
In the semiconductor capacitive element constructed as set forth, the HSG is formed on the surface of the amorphous silicon film 12 to be the lower electrode to increase the surface area. Therefore, the accumulated charge amount of the lower electrode can be increased.
Next, a method for forming the HSG on the surface of the amorphous silicon film 12 will be explained. As a fabrication process of the HSG, there are an annealing method disclosed in Japanese Unexamined Patent Publication No. 5-90490 and a nucleus forming method as disclosed in Japanese Unexamined Patent Publication No. 5-304273. At first, discussion will be given for annealing method.
As shown in FIG. 1B, in the annealing method, after formation of the amorphous silicon film 12, without removing the substrate from a layer deposition chamber while maintaining the chamber at a layer deposition temperature under reduced pressure, the HSG is formed. Specifically, after forming the amorphous silicon film 12 at a layer deposition temperature of 570.degree. C. under 0.2 Torr of pressure, heat treatment is subsequently effected under a reduced pressure for one hour to form the HSG on the surface of the amorphous silicon film 12. The annealing method is advantageous because forming the HSG can be achieved by using only the layer deposition furnace.
It should be noted that the HSG technology is a technology in which silicon atom on the surface of the amorphous silicon film is migrated by heat treatment to form clusters on the surface for forming surface unevenness. Migration of silicon atoms is significantly lowered by presence of contaminant, such as a natural oxidation layer, or the like, on the surface of the amorphous silicon film. Since the annealing method is a technology of performing heat treatment after deposition of the amorphous silicon film without taking the device out of the layer deposition chamber a, clean surface can be easily obtained before heat treatment. Accordingly, when the condition, such as temperature, pressure and so forth, in the chamber is constant, the HSG can be formed stably without any contamination from, for example, natural oxide.
Next, discussion will be given for nucleus forming method. The semiconductor substrate, on which the amorphous silicon film is formed, is mounted within the chamber (not shown). Disilane gas is introduced into the chamber to perform heat treatment for this substrate at a temperature of about 600.degree. C. By this, crystal nucleus of the HSG is formed on the surface of clean amorphous silicon film. Next, without removing from the chamber (not shown), annealing is performed. The annealing is performed at the same temperature as the temperature fore forming the crystal nucleus of the HSG, or at a maximum of 650.degree. C. Thus, silicon molecule form on the surface of amorphous silicon film surrounding the crystal nucleus, by migration, and aggregate to form the HSG on the surface of the amorphous silicon film.
Such nucleus forming method is implemented by two separate steps including a step of forming crystal nucleus of the HSG using a silane type gas and a step of annealing without introducing a layer deposition gas. Accordingly, the nucleus forming method is advantageous to control the grain diameter of the HSG by controlling the annealing condition in the annealing step, for example.
On the other hand, when the step of forming crystal nucleus is implemented under a pressure lower than or equal to 1 Torr, crystal nucleus is not formed on the silicon oxide layer and is only formed on the surface of the amorphous silicon film. Accordingly, the nucleus forming method is advantageous for capability of control of the forming density of the HSG by controlling a forming condition in the crystal nucleus forming step.
FIGS. 2A to 2C are sections showing process steps of one example of fabrication process of the HSG by nucleus forming method in sequential order. In FIGS. 2A to 2C, like elements to those in FIGS. 1A to 1E will be identified by like reference numerals, and detailed description therefor will be neglected. At first, in the similar manner to the method shown in FIGS. 1A and 1B, within the layer deposition chamber (not shown), the amorphous silicon film 12 is formed on the surfaces of a substrate 10 and a silicon oxide layer 11 which is selectively formed on the surface of the substrate.
Next, after taking the substrate out of the layer deposition chamber, as shown in FIG. 2A, utilizing lithographic technology and dry etching technology, the amorphous silicon film 12 is patterned to form a patterned amorphous silicon film 12b.
Subsequently, after mounting the substrate within the layer deposition chamber, the HSG is formed on the surface of the patterned amorphous silicon film 12b by way of nucleus forming method. At this time, since the forming condition of the crystal nucleus is appropriately controlled, the crystal nucleus is not formed on the silicon oxide layer 11. Thus, the lower electrode 12a is formed.
The process steps after formation of the HSG is similar to those in the annealing method. Namely, as shown in FIG. 2C, the silicon nitride layer (not shown), the capacitance insulation layer, is deposited to a thickness of about 7 nm on the lower electrode 12a. Then, on these surfaces, the upper electrode 13 of the capacitive element made of polycrystalline silicon is deposited. Thus, the semiconductor capacitive element is obtained.
The HSG forming method shown in FIGS. 2A to 2C is a method for forming the crystal nucleus in the condition where the crystal nucleus is formed only on the surface of the amorphous silicon film. Accordingly, after patterning the amorphous silicon film 12 to form the patterned amorphous silicon film 12b, the HSG can be formed on the surface of the patterned amorphous silicon film 12b. By this, the HSG is also formed on the side surface of the patterned amorphous silicon film 12b. Therefore, the nucleus forming method as shown in FIGS. 2A to 2C can further to increase the surface area of the lower electrode in comparison with the annealing method.
Thus, in the case where the HSG is formed by the conventional methods on the surface of amorphous silicon film, good shape of the HSG can be formed when the amorphous silicon film is not doped or has low impurity concentration where phosphorous concentration is lower than or equal to about 5.times.10.sup.19 (atoms/cm.sup.3).
However, when the HSG is formed by the conventional method utilizing amorphous silicon film having low impurity concentration, the following problems are encountered. FIG. 3 is a graph showing a relationship between capacitance and bias voltage with taking the capacitance with respect to the maximum capacitance in the vertical axis and bias voltage to be applied to the upper electrode in the horizontal axis. In FIG. 3, a solid line 1 shows variation of capacitance of the capacitive element formed with the HSG on the surface of amorphous silicon film having P-type impurity concentration of 5.times.10.sup.19 atoms/cm.sup.3). On the other hand, in FIG. 3, the broken line 2 shows variation of the capacitance of the capacitive element forming amorphous silicon film having p-type impurity concentration of 1.times.10.sup.20 (atoms/cm.sup.3), in which the HSG is not formed on the surface of the silicon film.
As shown by solid line in FIG. 3, when a positive bias is applied to the upper electrode, if the impurity concentration in the amorphous silicon film (lower electrode) is low, depletion layer is widened to lower effective capacitance. On the other hand, as shown by broken line 2, when the impurity concentration is increased in the amorphous silicon film, even if the bias is applied to the upper electrode, only a little drop of the capacitance is caused.
Namely, even when the surface area of the amorphous silicon film doubles by forming the HSG, if the capacitance value is lowered in the proportion of 30% by widening of the depletion layer, the actual increase of the capacitance value becomes only 1.4 times. Accordingly, when the charge accumulation amount of the capacitive element is to be increased by forming the HSG on the surface of the amorphous silicon film, higher impurity concentration in the amorphous silicon film is desirable. When the impurity concentration is higher than or equal to 1.times.10.sup.20 (atoms/cm.sup.3), widening of the depletion layer can be suppressed.
On the other hand, when the HSG is formed on the amorphous silicon film by the conventional process with utilizing the amorphous silicon film having high impurity (phosphorous) concentration, such as higher than or equal to 1.times.10.sup.20 (atoms/cm.sup.3), is used, the following problems exist. Namely, when the HSG is formed on the surface of the amorphous silicon film having high impurity concentration, the forming period of the crystal nucleus of the HSG and surface migration period of silicon molecule becomes longer in comparison with the case where non-doped amorphous silicon film is used. Thus, the density and the average grain size of the HSG formed becomes smaller.
On the other hand, in the case of forming the amorphous silicon film doped with the impurity, such as phosphorous or the like, crystallization speed of the bulk is higher than that of the non-doped amorphous. Accordingly, when a temperature for forming the HSG is elevated or a period for forming the HSG is prolonged, the amorphous silicon film may be crystallized from the substrate side during the HSG forming process. Then, crystallization reaches the surface of the silicon film before the HSG is formed, surface migration of the silicon molecule for forming the HSG is blocked and causes failure of HSG formation.
From this fact, when the HSG is formed on the surface of the amorphous silicon film doped with the impurity, and if it is desired to form good shape of the HSG, it is preferred that the forming condition is high temperature and long period. On the other hand, for avoiding occurrence of failure of formation of the HSG due to crystallization of the amorphous silicon film, the desirable forming condition is low temperature and short period. As a result, when the HSG is formed on the amorphous silicon film having high impurity concentration, the forming condition becomes significantly narrow. Accordingly, in the prior art, it has been difficult to form the HSG on the surface of the electrode (amorphous silicon film) having high impurity concentration.
In order to solve such problem, there is a method, in which an amorphous silicon film having low phosphorous concentration is formed, the HSG is formed on the surface thereof, and then phosphorous is doped in the amorphous silicon film by way of ion implantation or the like. By this it becomes possible to form the electrode (amorphous silicon film) having high impurity concentration, with the HSG on the surface.
However, when ion implantation is performed after formation of the HSG on the surface of the amorphous silicon film, the HSG crystal can be broken by ion implantation. By this, the surface of the amorphous silicon film formed with the HSG may return to an original flat surface. Accordingly, even when the impurity concentration in the amorphous silicon film is increased by ion implantation, capacity cannot be increased sufficiently because the HSG is destroyed by the ion implantation.